Although there has been considerable activity in the art of printed circuit boards, high density printed circuitry is a relatively recent area of investigation. Only recently have materials and processes been developed which can be used to provide the demanding electrical and mechanical properties required by high density configurations. High density packaging configurations are required in order to furnish fast access to large amounts of data in the next generation of computers, such as in supercomputers. The requirement of high density includes the necessity of increased wiring density and thinner dielectric layers for enhanced dimensional control. Conducting layers are electrically connected by vias and through-holes of increasingly narrow diameter. The term vias is normally used to describe conductive pathways within the circuit board which connect adjacent conductive layers. The term through-hole is normally used to describe vias which extend to non-adjacent conductive layers. The term blind via is sometimes used to refer to a through hole which terminates internally. For the sake of brevity, the term through-hole may hereinafter be used to refer to both.
High performance packaging refers to circuit cards and boards with very high wiring densities and via densities, which are typically made of insulating layers comprising a high performance dielectric material, i.e. having a dielectric constant (Er) of about 3.2 or less, at least in the signal line area, in order to reduce signal propagation delays and reduce signal noise and attenuation. A dielectric constant of 3.2 or less also permits reduction in signal-to-power spacings. In the present invention, the term high density typically refers to dimensions of the following approximate values in a printed circuit card or board:
______________________________________ Line Width 50 Microns (Approx. 2. mils) Line Thickness 12.5 Microns (Approx. 0.5 mils) Via Diameter 63 Microns +/-25 Microns (2.5 +/-1.0 mil) Land Diameter 120 Microns (4.7 mils) Clearance Hole 170 Microns (6.7 mils) Core Thickness 127 Microns (5.0 mils) ______________________________________
Packaging chips in a surface mount mode, called also direct chip attach (DCA), can require wiring densities exceeding several thousand inches per square inch and via densities which can exceed 10,000 vias per square inch for very high I/O chips in close proximity.
A high density circuit board having the abovementioned dimensions would be capable of providing wiring capability of approximately 100 inches per share inch per wiring plane and via densities of about 5,000 to about 10,000 vias per square inch. The total wiring requirement would be satisfied by adding a sufficient number of wiring planes to accommodate the number of chips. The small diameter via typically required precludes building such a high density board through traditional multilayer lamination and drill processes. In order to produce wiring and via densities of this magnitude, stacked via method are used. A stacked via board is a board which is made up of individual 2S1P (two signal planes plus one power plane) units joined at the vias to provide communication between 2S1P units. A structure, and a process for encapsulating 2S1P units and joining them to each other is a primary concern of this invention.
Suitable materials which can be used to provide an Er of 3.2 or below include fluorocarbons such as, for example, polytetrafluoroethylene (PTFE), polychlorotrifluoroethylene (CTFE), and polyperfluoropropylene, optionally filled with a filler, such as certain kinds of quartz or silicon particles, and optionally reinforced with fabric such as woven fluorocarbon fabric. The adhesion between fluorocarbons and metals is problematic, as well as are techniques for providing through holes of about 1.5 mils (0.038/mm) to about 3.5 mils (0.0889 mm) in diameter, which must be aligned between layers. Conductor lines are in the range of about 50 microns in width.
In circuit boards which do not have the stringent dimensional requirements of high density circuit boards, alignment of through holes from layer to layer is made indirectly, by aligning mechanical location slots which are peripheral to the function of the device and are placed over locating pins in order to align multiple layers. However, in high density circuit boards, the denser circuitry, finer conductor line and track width, thinner dielectric layers, greater number of layers and denser placement of smaller diameter holes and vias require an absolute, dead-on alignment from layer to layer that is not attainable through means that were satisfactory in the past. In the high density circuitry of the future, through-hole tolerance is such that a small misalignment can mean that there is no electrical interconnection at all, or a high resistance interconnection, between the layers where low resistance contact is required. The alignment of wire cores to each other is thus seen to be a very demanding registration operation requiring optical registration at the key registration step, viz. drilling, exposing circuitry, laminating layers together. This alignment is currently verified by means of attachment coupled with x-ray examination. Alignment problems are discussed in U.S. Pat. No. 4,788,766 issued Dec. 6, 1988 to Burger et al, which describes 2.00 ppm cap shrinkage during processing. Cap shrinkage can significantly affect alignment and becomes especially important at the time when the chip is mounted.
In addition, process flows in the cap manufacturing process typically can include a large number of steps, as many as eight or more, in order to join just two cores, whereas the present invention involves a significant reduction in process steps.
The present invention reduces the need for x-ray verification of alignment since alignment can be verified electrically on a subcomposite level.
Even in the past, problems in layer alignment where vias are about 15 mils or less in diameter were noted. In U.S. Pat. No. 4,566,186 issued Jan. 28, 1986 to Bauer et al, a method is described which includes applying a layer of photoimageable dielectric over a silk screened conductive polymer thick film, which is comprised of a metal dispersed in a polymer. Vias are exposed in the photoimageable dielectric, permitting vias to be as small as about 1 to about 5 mils in diameter. A solder masking step is also included. The techniques and materials described in the '186 patent, however, such as silk screening, would be inapplicable to the dimensions of the high density printed circuit board of the present invention. Also, the present invention does not employ a thick conductive polymer.
U.S. Pat. No. 3,934,335 issued Jan. 27, 1976 to Nelson describes a number of sources of alignment problems and known attempted solutions. The '335 patent describes the use of a photosensitive dielectric material in a process that seeks to avoid alignment problems and eliminates drilling from layer to layer by applying successive layers of photoactive dielectric, upon which circuit conductors are applied, and exposing and developing via openings and circuitry patterns therein. In the present invention, dielectric material, which may be photosensitive, is applied over existing wire core circuitry in order to encapsulate the circuitry on the 2S1P structure. It is not used as a base upon which circuit conductors are applied, nor as a dielectric layer between signal and power layers. It is, however, a dielectric layer between adjacent signal layers, i.e. between S2 and S3, between S4 and S5, etc.
U.S. Pat. No. 4,648,179 describes simultaneous bonding at pads of vias filled with bonding metallurgy and lamination of polyimide dielectric of a core to like structures of a second core as a way of avoiding registration problems. The present invention does not require the pad to pad alignment, but is self aligning by way of the bonding metallurgy itself.
Nowhere in the art is the method or structure of the present invention described, wherein a dielectric material encapsulates each high density wire core, and wherein encapsulated high density cores are aligned, using the joining metal for alignment, to test on the subcomposite level and build up a high density printed circuit card or board. Furthermore, while the dielectric of the present invention may be photoactive, it need not be.